Semiconductor structures comprising three-dimensional arrays of chips have emerged as an important packaging approach. A typical three-dimensional electronic structure consists of multiple integrated circuit chips having main planar surfaces adhesively secured together to form a monolithic structure (referred to as a "stack" or "cube"). A metallization pattern is often provided directly on one or more edge surface of the multichip stack for interconnecting the chips and for electrical connection of the stack to external circuitry. This exposed metallization pattern can include both individual input/output (I/O) connects and bussed connects.
Electrostatic discharge (ESD) is a phenomenon known to degrade or destroy discrete electronic components. In particular, given the decreasing size of circuit features with ever improving process technology, static electricity can destroy or substantially harm many of today's integrated circuits. Triboelectric charges are produced anytime two surfaces are separated and if at least one of the surfaces is a nonconductor, then a static electric charge is produced. This is a natural phenomenon and only causes a problem if the static charge is allowed to discharge or induce a charge into the integrated circuit. Such an ESD event can occur very pervasively to a point of several thousand volts. The discharge occurs very rapidly and the usual failure or degradation is caused by the gasification of metal within the device resulting in the gasified metal becoming deposited along a trace of the discharge path.
The damage following each electrostatic discharge event may be instantly catastrophic. Often times, however, the integrated circuit does not totally fail, but rather, remains operable with a latent defect that will ultimately result in premature failure. Such events can also alter the operating characteristics of the integrated circuit, thereby resulting in unsatisfactory and often unpredictable operation. Electrostatic discharge between input/output connects of a semiconductor device chip can occur, for example, from human handling, automated circuit testing or during packaging of discrete integrated circuit chips.
It has now been discovered that during three-dimensional multichip fabrication, an ESD failure can occur chip-to-chip, for example, during side surface processing of the cube whenever a voltage potential is established between two adjacent chips. This can lead to arcing from the transfer metal pins of one chip to the substrate or transfer metal pins of the adjacent chip resulting in an electrostatic discharge event. An ESD event can also be generated during testing of a multichip semiconductor stack between the testing tool and stack metallization or an integrated circuit chip substrate within the structure, which can subsequently result in a chip-to-chip ESD event.
Most, if not all, known electrostatic discharge protection networks operate in connection with a single semiconductor device chip. Since electrostatic discharge suppression circuitry can comprise ninety (90%) percent of the load on an input/output node, there is a need in the art for optimization of such circuitry within a three-dimensional multichip structure. More generally stated, there exists a need in the multichip packaging art for an approach to optimizing performance of the three-dimensional structure by deleting or consolidating redundant circuitry. The concepts, circuits and methods presented herein address this need.